preliminary p521 - 29 low phase noise lvds vcx o (100mhz to 200mhz) 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 rev 3/02/04 page 1 features 100mhz to 200 mhz fundamental mode crystal. output range: 100mhz ? 200mhz. complementary lvds outputs. selectable oe logic (enable high or enable low). integrated variable capacitors. high pull linearity: < 5%. +/ - 125 ppm pull range supports 2.5v or 3.3v - power supply. available in die form. thickness 10 mil. descriptions p521 - 29 is a vcxo ic specifically designed to pull high frequency fundamental crystals. its internal varicaps allow an on chip frequency pulling, controlled by the vcon input. the chip provides a low phase noise, low jitter lvds differential clock output. block diagram die configuration die specifications name value size 56.5 x 57.5 mil reverse side gnd pad dimensions 80 micron x 80 micron thickness 10 mil output enab le logic selection oesel (pad #14) oectrl (pad #22) state 0 tri - state 0 (default) 1 (default) output enabled 0 (default) output enabled 1 1 tri - state pad #14, 22: bond to gnd to set to ?0?, bond to vdd to set to ?1? no connection results to ?default ? setting through internal pull - up/ - down. pad #22: logical states defined by cmos v ih and v il levels. x+ x- oe q P521-29 vcon q oscillator amplifier w/ integrated varicaps 18 21 y x (0,0) (1460,1435) 56.5 mil 57.5 mil 19 20 22 1 2 3 4 6 13 14 11 17 16 15 12 10 9 8 7 5 gndbuf pecl peclbar vddbuf vddbuf vddana oe xout xin vcon gndosc gndbuf gndana gndosc vcon gndana n/c vddosc n/c oscoff oesel v gndbuf
preliminary p521 - 29 low phase noise lvds vcx o (100mhz to 200mhz) 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 rev 3/02/04 page 2 pad assignment and description pad # name x ( m m m) y ( m m m) description 1 vcon 329.6 110.1 control voltage input. use this pin to change the output freque ncy by varying the applied control voltage. 2 gndosc 498.3 110.0 gnd connection for oscillator circuitry. 3 gndana 696.2 110.0 gnd connection for analog circuitry. 4 gndana 825.0 110.0 gnd connection for analog circuitry. 5 gndbuf 973.6 110.0 gnd conne ction for output buffer circuitry. 6 gndbuf 1150.0 109.1 gnd connection for output buffer circuitry. 7 gndbuf (optional) 1183.6 302.2 gnd connection for output buffer circuitry. 8 lvds 1183.6 452.3 lvds output 9 lvdsbar 1183.6 613.5 lvds complementary output. 10 vddbuf (optional) 1182.4 745.9 vdd connection for output buffer circuitry. vddbuf should be separately decoupled from other vdds whenever possible. 11 vddbuf 1252.4 903.6 vdd connection for output buffer circuitry. vddbuf should be separately decoupled from other vdds whenever possible. 12 vddana 1252.4 1081.3 vdd connection for analog circuitry. vddana should be separately decoupled from other vdds whenever possible. 13 not used 1058.5 1221.6 14 oesel 864.5 1221.6 selector input to choose the oe control logic. see table on page 1. 15 vddosc 624.0 1222.7 vdd connection for oscillator circuitry. vddosc should be separately decoupled from other vdds whenever possible. 16 not used 467.1 1222.6 17 oscoff 271.1 1222.6 oscillator off selection input pad. when low, turns off the oscillator when output is disabled. when high (default), oscillator running when output is disabled. internal pull - up 18 gndosc (optional) 109.4 1222.9 gnd connection for oscillator circuitry. 19 vcon 108.9 1062.1 cont rol voltage input. use this pin to change the output frequency by varying the applied control voltage (internally connected to pad 1). 20 xin 109.0 865.8 crystal oscillator input pad. 21 xout 108.6 358.4 crystal oscillator output pad. 22 oectrl 108.6 14 6.5 oe input pad. see table on page 1. note: for optimal phase noise performance, it is recommended to bond all optional vdd and gnd pads.
preliminary p521 - 29 low phase noise lvds vcx o (100mhz to 200mhz) 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 rev 3/02/04 page 3 electrical specifica tions 1. absolute maximum ratings parameters symbol min. max. units supply voltage v dd 7 v input voltage, dc v i v ss - 0.5 v dd +0.5 v output voltage, dc v o v ss - 0.5 v dd +0.5 v storage temperature t s - 65 150 c ambient operating temperature t a 0 70 c junction temperature t j 125 c lead temperature (soldering, 10s) 260 c input static discharg e voltage protection 2 kv exposure of the device under conditions beyond the limits specified by maximum ratings for extended periods may cause permanent damage to the device and affect product reliability. these conditions represent a stress rating on ly, and functional operations of the device at these or any other co n ditions above the operational limits noted in this specification is not implied. 2. crystal specifications parameters symbol conditions min. typ. max. units crystal resonator frequency f xin parallel fundamental mode 100 200 mhz crystal loading rating c l (xtal) die at vcon = 1.65v 7.5 pf interelectrode capacitance c 0 3.5 pf crystal pullability c 0 /c 1 (xtal) at cut 250 - recommended esr r e at cut 30 w 3. voltage control crystal oscillator parameters symbol conditions min. typ. max. units vcxo stabilization time * t vcxostb from power valid 10 ms vcxo tuning range xtal c 0 /c 1 < 250 250* ppm clk output pullability 0v vcon 3.3v at room temper ature 80* ppm on - chip varicaps control range vcon = 0 to 3.3v 4 ? 18* pf linearity 4* 5* % vcxo tuning characteristic 65 ppm/v vcon input impedance 60 k w vcon modulation bw 0v vcon 3.3v, - 3db 25 khz note: parameters denoted wi th an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
preliminary p521 - 29 low phase noise lvds vcx o (100mhz to 200mhz) 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 rev 3/02/04 page 4 4. general electrical specifications parameters symbol conditions min. typ. max. units supply current (loaded outputs) i dd at 3.3v @ 155mhz 45 ma oscillator off 10 output valid after oe enabled oscillator on 1 ms operating voltage v dd 2.25 3.63 v output clock duty cycle @ 1.25v (lvds) 45 50 55 % short circuit current 50 ma 5. jitter specifications parameters c onditions min. typ. max. units period jitter rms at 155mhz 2.5 period jitter peak - to - peak at 155mhz at 155.52mhz, with capacitive decoupling b e tween vdd and gnd. over 10,000 cycles 18.5 20 ps accumulated jitter rms at 155mhz 2.5 accumulated jitter peak - to - peak at 155mhz at 155.52mhz, with capa citive decoupling b e tween vdd and gnd. over 1,000,000 cycles. 24 27 ps random jitter ?rj? measured on wavecrest sia 3000 2.5 ps integrated jitter rms at 155mhz integrated 12 khz to 20 mhz 0. 25 0. 35 ps measured on wavecrest sia 3000 6. phase noise specifications parameters frequency 10hz 100hz 1khz 10khz 100khz 1mhz units phase noise relative to carrier 155.52mhz - 75 - 100 - 125 - 140 - 145 - 150 dbc/hz note: phase noise measured at vcon = 0v
preliminary p521 - 29 low phase noise lvds vcx o (100mhz to 200mhz) 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 rev 3/02/04 page 5 7. lvds ele ctrical characteristics parameters symbol conditions min. typ. max. units output differential voltage v od 247 355 454 mv v dd magnitude change d v od - 50 50 mv output high voltage v oh 1.4 1.6 v output low voltage v ol 0.9 1.1 v offset voltage v os 1.125 1.2 1.375 v offset magnitude change d v os r l = 100 w (see figure) 0 3 25 mv power - off leakage i oxd v out = v dd or gnd v dd = 0v 1 10 ua output short circuit current i osd - 5.7 - 8 ma 8. lvds switching characteristics parameters symbol conditions min. typ. max. units differential clock rise time t r 0.2 0.7 1.0 ns differentia l clock fall time t f r l = 100 w c l = 10 pf (see figure) 0.2 0.7 1.0 ns out out v od v os 50 w 50 w out v diff r l = 100 w c l = 10pf c l = 10pf lvds switching test circuit lvds levels test circuit lvds transistion time waveform out out out 0v (differential) 0v 20% 80% 20% 80% t r t f v diff
preliminary p521 - 29 low phase noise lvds vcx o (100mhz to 200mhz) 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 rev 3/02/04 page 6 ordering information phaselink corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. the information furnished by phaselink is believed to be accurate and reliable. however, phaselink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. li fe support policy : phaselink?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of phaselink corporation. part number the order number for this device is a combination of the following: device number, package type and operating temperature range p521 - 29 d c order number marking package option p 521 - 29d c p521 - 29dc die ? waffle pack part n umber temperature c=commercial package type d=die
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